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AR# 62609

MIG 7 Series DDR - RDIMM initialization sequence violates JESD82-29A spec


Version Found: MIG 7 Series v2.2

The JESD82-29A RDIMM specification states:

"A certain period of time (tACT) before the RESET# input is pulled HIGH the reference voltage needs to be stable within
specification, the clock input signal must be stable, the register inputs DCS[n:0]# must be pulled HIGH to
prevent accidental access to the control registers and DCKE0 as well as DCKE1 must be pulled LOW."

However MIG holds cs_n low throughout the initialization sequence, and later releases it along with cke:



As stated above, the spec requires that cs_n is pulled high during reset to prevent access to the control word registers. 

However, a control word access requires both cs_n driven high and cke driven low:

Bits DA[15:5] must be LOW and at least one DCKEn input must be HIGH for a valid access. 

During control word write, at least one DCKEn must be asserted.

Since the MIG controller holds CKE low throughout the duration of the initialization sequence, it is not possible for the control registers to be written to and hence no issues will be seen in hardware.

Revision History
10/24/2014 - Initial Release

AR# 62609
Date Created 10/24/2014
Last Updated 12/04/2014
Status Active
Type General Article
  • Kintex-7
  • Artix-7
  • Virtex-7
  • Vivado Design Suite - 2014.3
  • MIG 7 Series