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AR# 62627

SRIO - clocking for V5 is specified incorrectly in the UG503


The Serial RapidIO (SRIO) user guide (UG503) has the clocking for Virtex-5 specified incorrectly. 

For both Virtex-6 and Virtex-4 devices, the UCLK_DIV4 clock domain is set to 4 times the period of the UCLK domain.

However in the Virtex-5 section, both UCLK and UCLK_DIV4 are set to the same period.


This is a mistake in the documentation.

The example design follows this documentation for its constraints.

This should also be corrected in the example design.

AR# 62627
Date Created 10/28/2014
Last Updated 11/04/2014
Status Active
Type General Article
  • Virtex-5
  • Serial RapidIO