We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62639

14.x CORE Generator - WARNING:coreutil - Failed to generate file: core_v


I am getting the following error when trying to generate a clk_wiz_v3_6 core in CORE Generator:

WARNING:coreutil - Failed to generate file: core_v
       invoked from within
   "deliverEJava $componentName GenerationOptions $TopLevel"
       (procedure "components::clk_wiz_v3_6::generate" line 36)
       invoked from within
       (procedure "::xilinx::sim::generation::generateCore3rdParty" line 125)
       invoked from within
       (procedure "main" line 25)
       invoked from within
   "main $argc $argv"
       invoked from within
   "return [main $argc $argv]"
   _6\generate\run_legacy_tcl_flow.tcl" line 47)ERROR:sim - Unable to evaluate Tcl file:


In the coregen.log file, when debugging is turned on (-ddd), the following message is seen just before the error:

Picked up _JAVA_OPTIONS: -Djava.net.preferIPv4Stack=true

This environment variable is conflicting with the operations required by Coregen.

Removing this environment variable will allow Coregen to generate the core.

AR# 62639
Date Created 10/28/2014
Last Updated 01/15/2015
Status Active
Type General Article
  • ISE Design Suite
  • ISE Design Suite - 14
  • ISE Design Suite - 14.7