UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62649

MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selected

Description

Version Found: MIG UltraScale v6.0
Version Resolved: See (Xilinx Answer 58435)

The MIG UltraScale GUI allows core generation with invalid Bank/Byte selection (for example where Addr/Cntrl-2 is left unassigned) which can lead to placer errors such as the following:

[Place 30-687] Expected cell DDR4_1/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice be placed along with its associated I/O.
Please check if the cell is properly connected to any I/O.

Solution

To ensure valid Bank and Byte selection, open the MIG I/O Planner and run "Report DRC".

If no DRC errors are detected in the I/O Planner then proceed with IP core generation.

Revision History:
10/29/2014 - Initial Release

Linked Answer Records

Master Answer Records

AR# 62649
Date Created 10/29/2014
Last Updated 11/05/2014
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale