We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62666

Ethernet 1000BASE-X PCS/PMA or SGMII - v14.3 - 2014.3 -7 Series GTX/GTH - Intermittent link up failures seen


When updating to Ethernet 1000BASE-X PCS/PMA or SGMII v14.3 released in Vivado 2014.3, intermittent link up failures are seen out of reset when targeting 7 Series GTX/GTH transceivers.


This failure was introduced in the v14.3 release in 2014.3 and is fixed in the v14.3 (Rev. 1) release in 2014.4.

To work around the failure in the v14.3 core in Vivado 2014.3, lock the core and make the following changes:

1.   core_name_gtwizard_gt

  • Replace drpclk_in with cplllockdetclk_in.
    cplllockdetclk_in is tied to the stable clock used in reset fsms.

2.  core_name_gtwizard_init

  • Remove cpll_reset_sync
  • Connect gt0_cpllreset_i to gt0_cpllreset_in the port of the gtwizard_i instance.

3.    core_name.xdc

  • Remove this false path constraint:

 set_false_path -to [get_pins -hier -filter { name =~ */gtwizard_inst/*/cpll_reset_sync/reset_sync*/PRE } ]

For information on locking the core so that the changes are not over-written, see (Xilinx Answer 57546).

AR# 62666
Date Created 10/31/2014
Last Updated 11/24/2014
Status Active
Type General Article
  • Ethernet 1000BASE-X PCS/PMA or SGMII