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AR# 62693

Aurora 64B66B v9.2 Rev1 or earlier - gt_reset_i_tmp not routed to reset_i in example design without lab tools


In the example design the "pma_init" staging is done with a 128 cycle delay to make sure 'reset' is asserted 128 user_clk cycles before 'pma_init'.

If the Vivado Lab Tools are selected, "gt_reset_i_tmp" is routed back to the 'reset' input to make sure 'reset' is asserted before "pma_init".

When the Lab Tools are not selected, this feedback is not present.

As a result, the reset sequence is different for the two setups.


In the aurora_64b66b_0_exdes.v file, update the code as shown below.

This will ensure that the reset sequence is followed:
Existing code:
assign  reset_i = system_reset_i;
Modified code:
   wire gt_reset_i_tmp2;
      aurora_64b66b_0_rst_sync_exdes   u_rst_sync_gtrsttmpi
       .prmry_in     (gt_reset_i_tmp),
       .scndry_aclk  (user_clk_i),
       .scndry_out   (gt_reset_i_tmp2)
   assign  reset_i = system_reset_i | gt_reset_i_tmp2;


This is a known issue with Aurora 64B66B v9.2 Rev1 or earlier and is fixed with the v9.3 release in Vivado Design Suite 2014.3.

Revision History:

11/04/2014 - Initial Release

AR# 62693
Date Created 11/03/2014
Last Updated 11/11/2014
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Aurora 64B/66B