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AR# 62721

2014.2 Vivado Write_bitstream - DRC check "LUT Flip Flop Pairs over-utilized" for fully placed design should be skipped


A case has been seen where a design was targeted to 7V550T, the implementation completed with no errors and the utilization report showed no problems with resource utilization. 

However, when running write_bitstream, DRC flagged the following utilization issue:

ERROR: [Drc 23-20] Rule violation (UTLZ-1) Resource utilization - LUT Flip Flop Pairs over-utilized in Pblock ROOT (This design requires more LUT Flip Flop Pairs cells than are available in the target device. This design requires 376892 of such cell types but only 346400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)

How can this be resolved?


For a fully placed design, an over-utilization check of LUT Flip Flop Pairs does not make sense, so the DRC check should be disabled. 

This has been fixed for Vivado 2014.4.

In the meantime, To work around this issue, you can use the following command to disable the check before write_bitstream:

set_property IS_ENABLED FALSE [get_drc_checks UTLZ-1]
AR# 62721
Date Created 11/05/2014
Last Updated 11/17/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3