A case has been seen where a design was targeted to 7V550T, the implementation completed with no errors and the utilization report showed no problems with resource utilization.
However, when running write_bitstream, DRC flagged the following utilization issue:
How can this be resolved?
For a fully placed design, an over-utilization check of LUT Flip Flop Pairs does not make sense, so the DRC check should be disabled.
This has been fixed for Vivado 2014.4.
In the meantime, To work around this issue, you can use the following command to disable the check before write_bitstream:
set_property IS_ENABLED FALSE [get_drc_checks UTLZ-1]