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AR# 62728

JESD204 - Subclass 0 clocking and glblclk_n / _p


For JESD204, if Subclass 0 operation is required, the timing limitations imposed to support deterministic latency are removed, and simplified clocking arrangements can be used which require only a reference clock input.
How should glblclk_p / _n be handled in this situation?


For Subclass 0 operation, it is possible to use the TXOUTCLK from the transceiver to generate the core clock.

glblclk_p / _n is optional in Subclass 0, the choice of refclk dictates whether or not it can be disabled in the IP GUI.
If the refclk frequency is equal to the coreclk frequency, then a single refclk can be used and glblclk is not required.

If the refclk frequency is not equal to the coreclk frequency, then "shared logic in example design" must be used, and the txoutclk needs to be manually wired to the coreclk. 

The standard clocking module generated is used as a starting point to create the required clocking configuration.
There is no GUI option available to do this.

Additionally, the clocking module should be modified to drive the BUFGs with the new inputs that have been added. 

These changes would be required for both Tx and Rx.

AR# 62728
Date Created 11/05/2014
Last Updated 11/06/2014
Status Active
Type General Article
  • JESD204