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AR# 62763

2014.3 Vivado Timing - 7-Series - No falling clock edge clock-to-out analysis for OSERDES


When I run "report_timing_summary" or "report_timing" on paths associated with OSERDES, I do not see the falling clock edge clock-to-out paths. 

How can I work around this?


The 7-Series timing model for the OSERDES is missing the falling clock edge clock-to-out timing arcs.  

The falling clock edge clock-to-out timing delays are the same as the rising clock edge clock-to-out timing delays, so the workaround is to use the rising clock edge values.

AR# 62763
Date Created 11/06/2014
Last Updated 11/17/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2014.3