I have a synthesized design which can be opened without issue.
However, when I set the mark_debug attribute on a net in the synthesized design and reopen the synthesized design with the following steps, an error occurs.
Steps to add mark_debug attribute:
This issue is fixed in Vivado 2014.3.
To work around this issue in Vivado 2014.2, you can export the DCP after setting the mark_debug attribute.
The generated DCP can be used for ILA inserting and implementation.