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AR# 62810

Vivado 2014.4, UltraScale Block Memory Generator- BRAM RDADDRCHANGE[A|B] setting option not available in Block Memory Generator GUI.


A new attribute RDADDRCHANGE[A|B] has been added for UltraScale block RAMs.
This attribute cannot be set via the Block Memory Generator (BMG) GUI (even with common clock enabled) and by default is set to FALSE.
How can I set this attribute via BMG?


The current version of the tools does not yet support the setting of this attribute.

For now the work-around is to either edit the HDL or use constraints to modify the setting.

For example:

set_property RDADDRCHANGEA TRUE [get_cells {BMG_PORT/bmg0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop.ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram}]
set_property RDADDRCHANGEB TRUE [get_cells {BMG_PORT/bmg0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop.ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram}]

This is planned to be fixed in Vivado 2015.1.
AR# 62810
Date Created 11/12/2014
Last Updated 02/23/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
  • Block Memory Generator