We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 6282

Logic Modeling - smartccn fails when using back-annotated EDIF created with .NGM file (error 11032: no package pin connected)


Keywords: LMG, SmartModel, smartccn, Synopsys, NGD2EDIF, NGDANNO, EDIF, NGM, 11032

When I attempt to compile a back-annotated EDIF file with Smartccn, the following error occurs:

***** Error: The design port (data_out<7:0>) has no package pin connected.
1 error, 540 warnings, smartccn 11032

This error only occurs when two situations exist. First, the .NGM file must be used when creating the back-annotated .NGA file, which is then used to create the back-annotated EDIF file. Second, the original EDIF file created by the design entry tool must be written with busses intact.

If these two conditions exist, then when the back-annotated EDIF file is produced, the correlation to the original design is done, pin assignments for busses will be lost. Since LMG needs all pin assignments to create the SmartCircuit model, the error will occur.


To work around this error, make sure that at least one of these two conditions are not met:

To instruct NGDANNO to NOT use the .NGM file (which is produced by MAP), open the Options
dialog in the Xilinx Design Manager (or Project Manager) and click on "Edit Options..." next to the
Simulation Template. Under the General tab, deselect the box next to "Correlate Simulation Data
to Input Design".


Instruct your design entry tool to expand all bus signals into their component bits when writing the
EDIF file for implementation. Methods for doing this will vary; consult your EDA tool documentation
for details.
AR# 6282
Date 10/31/2008
Status Archive
Type General Article