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AR# 62826

7 Series MIG - Jitter requirment for sys_clk input

Description

(UG586) states:

"sys_clk

This is the system clock input for the memory interface and is typically connected to a low-jitter external clock source."


Does MIG have a maximum jitter requirement defined for the sys_clk input?

Solution

No, MIG does not specify an input jitter requirement for sys_clk.  

The only requirement is that the Maximum Input Clock Period Jitter specification for the MMCM and PLL are met, as defined in the FPGA DC and AC Switching Characteristic Datasheet.

AR# 62826
Date Created 11/13/2014
Last Updated 01/07/2015
Status Active
Type General Article
IP
  • MIG 7 Series