We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62842

2014.3 System Management Wizard Synthesis of IP fails when the project language is VHDL and OT (Over Temperature Alarm) is disabled in the IP


Within the System Management IP, if VHDL is selected as the project language and the Over Temperature alarm is disabled the synthesis of the IP fails.

Also if the example design is generated for the same combination, the
compilation of the example design also fails.


This is a known issue with the system_management_wiz_v1_1 core and it will be fixed in a future version of Vivado Design Suite.

To work around the issue you can either:

  • Change the target language to Verilog.
  • Enable the OT alarm even if it is not used in your design and leave the port open when instantiating the core.
AR# 62842
Date Created 11/14/2014
Last Updated 11/18/2014
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale