The design contains a PP_RANGE constraint for all of the ports of RM.
Some ports of RM are driven within the RM, but are loadless in static logic.
The below DRC error will be caused by the issue:
These reported ports should not have a PP_RANGE, but this design has a custom PP_RANGE that applies to all pins.
The work-around is to remove the offending constraint from the correct pins using reset_property as shown below:
In the 2015.1 release of Vivado, the PP_RANGE for illegal pins will be removed automatically.