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AR# 62850

2014.4 Partial Reconfiguration - PPLOC error in router when the RM has output ports that are driven within the RM, but loadless in Static logic

Description

The design contains a PP_RANGE constraint for all of the ports of RM.

For Example:

   %set_property HD.PARTPIN_RANGE {SLICE_X2Y150:SLICE_X23Y159 SLICE_X40Y150:SLICE_X99Y159 SLICE_X86Y160:SLICE_X99Y198 SLICE_X100Y200:SLICE_X167Y209 SLICE_X148Y210:SLICE_X167Y248 SLICE_X148Y250:SLICE_X179Y259} [get_pins RM_submodule/*]

Some ports of RM are driven within the RM, but are loadless in static logic.

The below DRC error will be caused by the issue:

ERROR: [Constraints 18-900] HDPostRouteDRC-03: the non-boundary net RM_submodule/module4_rdat[15] has PPLOC INT_L_X56Y197/SE2BEG3 on it. All non-boundary nets must not contain any PPLOC

Solution

These reported ports should not have a PP_RANGE, but this design has a custom PP_RANGE that applies to all pins.

The work-around is to remove the offending constraint from the correct pins using reset_property as shown below:

  %reset_property HD.PARTPIN_RANGE [get_pins {RM_submodule/module4_rdat[15] RM_submodule/module4_rdat[14] RM_submodule/module4_rdat[13] RM_submodule/module4_rdat[12]  }]

In the 2015.1 release of Vivado, the PP_RANGE for illegal pins will be removed automatically.

AR# 62850
Date Created 11/16/2014
Last Updated 02/13/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4