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AR# 62852

MIG 7 series - GUI restricts selection of required clock period that was allowed in earlier verisons

Description

Version Found: MIG 7 Series v2.2

Version Resolved: See (Xilinx Answer 54025)


When configuring a MIG Controller at 800MHz for a 1.35V component, the following warning is generated in the GUI. 

This is preventing core generation:

The Memory Part ##### with the Voltage 1.35V supports the clock period range 1500 - 3300. Either change the clock period or select a different Memory Part Voltage

This worked in older versions of the MIG GUI but appears to be limited now. 

Solution

The MIG GUI should support the maximum frequency values listed in the FPGA AC & DC Switching Guide Datasheet.

See the "Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator" table for the respective device.

As a workaround, modify the PLLE2_ADV settings in the MIG design making sure that the device VCO frequency is met.

 

Revision History

11/25/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 62852
Date Created 11/17/2014
Last Updated 01/09/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.3
IP
  • MIG