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AR# 62854

7-Series PCI Express Solutions (Vivado 2014.3) - Excessive BUFG usage

Description

Tool Version Affected: Vivado 2014.3
Version Resolved and other Known Issues:

In Vivado 2014.3, a fix described in (Xilinx Answer 59294) was applied to all 7-series PCI Express cores listed below.

This change resulted in one BUFG per lane in PCI express cores created with Vivado 2014.3. 

However, the solution should have used only one BUFG per PCIe implementation, not per lane. 

Designs that use the 2014.3 version of PCIe cores will not have functional issues, but the extra BUFG usage may cause issues with some designs not having enough BUFGs to operate. 

  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express
  • AXI Bridge for PCI Express
  • 7 Series Integrated Block for PCI Express

Solution

This is a known issue, due to be fixed in the next release of the core in Vivado 2014.4.

To work around the issue, please install the corresponding patch attached with this answer record, as described below.

  •     These patches are only for Vivado 2014.3
  •     Unzip the attached zip file to the directory you choose.
  •     Open Vivado 2014.3 and create a new project.
  •     Open IP catalog. Right click on the core you are using and choose IP Settings.
  •     Click Add Repositories and point it to the location where you have unzipped the patch.
  •     Click OK and you are now ready to generate the core.
  •     If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  •     Alternatively, you could use the MYVIVADO environment variable and point this to the location of the patch.

Revision History:
11/20/2014 - Initial Release

Attachments

Associated Attachments

AR# 62854
Date Created 11/17/2014
Last Updated 11/20/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.3
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
  • AXI PCI Express (PCIe)