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AR# 62859

Vivado HLS - How to achieve PIPELINE II=1 of floating point accumulation?

Description

How can I achieve PIPELINE II=1 of floating point accumulation?

I am using the code below:
 
#define FT float
FT ybd(FT din[1024]){
FT sum=0;
LOOP:for(int i=0;i<1024;i++){
#pragma HLS PIPELINE
sum+=din[i];
}
return sum;
}

However HLS reports the following warning:
 

@W [SCHED-68] Unable to enforce a carried constraint (II = 9)
   between 'fadd' operation ('sum', ybd/ybd.cpp:7) and 'fadd' operation ('sum', ybd/ybd.cpp:7).


Solution

Because the latency of fadd in this case is 11 clock cycles, you will need to fill up and pipeline inside fadd so it does one addition every clock cycle.

XAPP599 covers this in detail.

Below is the modified code.

The II for the function is 1034:

#define FT float
#define FADD_LAT 11
FT ybd(FT din[1024]){
FT sum_p[FADD_LAT];
#pragma HLS ARRAY_PARTITION variable=sum_p complete dim=1
FT sum;

loop_init: for(int i=0;i<FADD_LAT;i++) {
#pragma HLS UNROLL
sum_p[i] = 0;
}
sum = 0;

LOOP:for(int i=0;i<1024;i+=FADD_LAT){
#pragma HLS PIPELINE II=11 rewind
for (int j=0; j<FADD_LAT; j++)
sum_p[j]+=din[j+i];
}

loop_sum_f: for (int k=0; k<FADD_LAT; k++)
{
#pragma HLS UNROLL
sum += sum_p[k];
}
return sum;
}

AR# 62859
Date Created 11/17/2014
Last Updated 11/26/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1