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AR# 62882

2014.4 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2014.4 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

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100G Ethernet (1.4)
 * Version 1.4
 * Support for xcvu160 and xcvu190 devices
 * Added Core DRP reset port
 * GT RX Buffer Bypass feature with Multi-Lane
32-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Added support for Artix7 xc7a15t and xa7a15t devices
 * Added support for Zynq xc7z035 device
 * Added support for QKintex7, AZynq, QZynq device family
3GPP LTE Channel Estimator (2.0)
 * Version 2.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
3GPP LTE MIMO Decoder (3.0)
 * Version 3.0 (Rev. 7)
 * Internal GUI update, no functional changes.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
3GPP LTE MIMO Encoder (4.0)
 * Version 4.0 (Rev. 6)
 * Internal GUI update, no functional changes.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
3GPP Mixed Mode Turbo Decoder (2.0)
 * Version 2.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
3GPP Turbo Encoder (5.0)
 * Version 5.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
3GPPLTE Turbo Encoder (4.0)
 * Version 4.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
64-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Added support for Artix7 xc7a15t and xa7a15t devices
 * Added support for Zynq xc7z035 device
 * Added support for QKintex7, AZynq, QZynq device families
7 Series FPGAs Transceivers Wizard (3.4)
 * Version 3.4 (Rev. 1)
 * Added SATA gen1 and SATA gen2 templates for GTX and GTP
 * Added support for XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices
 * Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices
 * Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices
7 Series Integrated Block for PCI Express (3.0)
 * Version 3.0 (Rev. 4)
 * Enhancement to allow debug cores to work better within Tandem designs. Build_stage1.tcl now runs before place_design and handles bscan primitives.
 * Added support for Artix7 xc7a15t, xc7a15tl and xa7a15t devices
 * Added support for Zynq xc7z035 device
 * Changed the pipe mode simulation options in GUI to radio buttons (No change in the functionality)
AHB-Lite to AXI Bridge (3.0)
 * Version 3.0 (Rev. 2)
 * No changes
AXI 10G-Ethernet Subsystem (2.0)
 * Version 2.0 (Rev. 1)
 * The AXI-Lite state machine in the example design is now repeatedly carrying out MDIO reads until it detects block lock in non pcs-loopback mode.
AXI AHBLite Bridge (3.0)
 * Version 3.0 (Rev. 2)
 * No changes
AXI APB Bridge (3.0)
 * Version 3.0 (Rev. 2)
 * No changes
AXI BFM Cores (5.0)
 * Version 5.0 (Rev. 4)
 * No changes
AXI BRAM Controller (4.0)
 * Version 4.0 (Rev. 3)
 * Internal device family change, no functional changes
 * Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
 * Reduced the IP INFO messages sent to the tool while creation of the IP
AXI Bridge for PCI Express Gen3 Subsystem (1.0)
 * Version 1.0 (Rev. 1)
 * Fix to properly pass the PCIe subsystem_vendor_id and subsystem_id to the PCIe hardblock.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Added support for UltraScale KintexU and VirtexU devices
AXI CAN (5.0)
 * Version 5.0 (Rev. 7)
 * Attribute addition to cdc flops, no functional changes
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
AXI Central Direct Memory Access (4.1)
 * Version 4.1 (Rev. 4)
 * No changes
AXI Chip2Chip Bridge (4.2)
 * Version 4.2 (Rev. 3)
 * Enhanced support for IP Integrator
AXI Clock Converter (2.1)
 * Version 2.1 (Rev. 3)
 * Internal device family change, no functional changes
AXI Crossbar (2.1)
 * Version 2.1 (Rev. 5)
 * Internal device family change, no functional changes
AXI Data FIFO (2.1)
 * Version 2.1 (Rev. 3)
 * Internal device family change, no functional changes
AXI Data Width Converter (2.1)
 * Version 2.1 (Rev. 4)
 * Internal device family change, no functional changes
AXI DataMover (5.1)
 * Version 5.1 (Rev. 5)
 * AXI Datamover example design updated to handle some corner cases
 * No functional changes
AXI Direct Memory Access (7.1)
 * Version 7.1 (Rev. 4)
 * No changes
AXI EMC (3.0)
 * Version 3.0 (Rev. 3)
 * Updated to support IPI automation for EMC_INTF interface
 * Updated the state-machine to remove the extra reads coming for Single axi transaction
AXI EPC (2.0)
 * Version 2.0 (Rev. 6)
 * No changes
AXI Ethernet Buffer (2.0)
 * Version 2.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
AXI Ethernet Clocking (2.0)
 * Version 2.0 (Rev. 1)
 * No changes
AXI Ethernet Subsystem (6.2)
 * Version 6.2 (Rev. 1)
 * Adding support for XC7Z035 and XC7A15T devices.
 * Adding support for XA/XQ device variants.
AXI EthernetLite (3.0)
 * Version 3.0 (Rev. 2)
 * No changes
AXI GPIO (2.0)
 * Version 2.0 (Rev. 6)
 * No changes
AXI HWICAP (3.0)
 * Version 3.0 (Rev. 7)
 * Updated core constraints to accommodate helper core (fifo_generator_v12_0) hierarchy updates. No functional changes.
AXI IIC (2.0)
 * Version 2.0 (Rev. 7)
 * Default values of Thigh, Tlow register updated to generate more accurate SCK clock frequency
AXI Interconnect (2.1)
 * Version 2.1 (Rev. 5)
 * Update IPI automation Tcl to allow import of BD files containing AXI Interconnect.  No functional changes.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
AXI Interrupt Controller (4.1)
 * Version 4.1 (Rev. 2)
 * No changes
AXI Lite IPIF (3.0)
 * Version 3.0 (Rev. 1)
 * Bus2IP address is handled correctly for overlapping write and read transactions
AXI MMU (2.1)
 * Version 2.1 (Rev. 2)
 * Internal device family change, no functional changes
AXI Master Burst (2.0)
 * Version 2.0 (Rev. 5)
 * No changes
AXI Memory Mapped To PCI Express (2.5)
 * Version 2.5 (Rev. 1)
 * Added support for Zynq xc7z035 device
 * Removed old ISE based XCS tags
AXI Memory Mapped to Stream Mapper (1.1)
 * Version 1.1 (Rev. 3)
 * Architecture support updated
AXI Performance Monitor (5.0)
 * Version 5.0 (Rev. 5)
 * In profile mode configuration of IP, issue handling metric calculation when write issuance and address issuance are very close is fixed
AXI Protocol Checker (1.1)
 * Version 1.1 (Rev. 5)
 * Internal device family change, no functional changes
AXI Protocol Converter (2.1)
 * Version 2.1 (Rev. 4)
 * Internal device family change, no functional changes
AXI Quad SPI (3.2)
 * Version 3.2 (Rev. 2)
 * No changes
AXI Register Slice (2.1)
 * Version 2.1 (Rev. 4)
 * Internal device family change, no functional changes
AXI TFT Controller (2.0)
 * Version 2.0 (Rev. 7)
 * Fixed Timing DRC in design, no functional changes.
AXI Timebase Watchdog Timer (2.0)
 * Version 2.0 (Rev. 6)
 * No changes
AXI Timer (2.0)
 * Version 2.0 (Rev. 6)
 * No changes
AXI Traffic Generator (2.0)
 * Version 2.0 (Rev. 5)
 * modified to generate continuous Index for MSTRAM, when master AXI interface Data width is greater than 64
 * Updated the RTL to correctly generate the done bit in STATIC mode, when transaction given is not accepted by slave and core disable is asserted
 * Corrected the GUI behavior for Sparse enablement in AXI-Streaming mode
AXI UART16550 (2.0)
 * Version 2.0 (Rev. 6)
 * No changes
AXI USB2 Device (5.0)
 * Version 5.0 (Rev. 5)
 * Disabled HSIC related parameters from GUI
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
AXI Uartlite (2.0)
 * Version 2.0 (Rev. 7)
 * Minor updates to example design. No functional changes.
AXI Video Direct Memory Access (6.2)
 * Version 6.2 (Rev. 2)
 * No changes
AXI Virtual FIFO Controller (2.0)
 * Version 2.0 (Rev. 6)
 * No changes
AXI-Stream FIFO (4.1)
 * Version 4.1 (Rev. 1)
 * Internal device family change, no functional changes
AXI4-Stream Accelerator Adapter (2.1)
 * Version 2.1 (Rev. 2)
 * No changes
 
AXI4-Stream Broadcaster (1.1)
 * Version 1.1 (Rev. 4)
 * Architecture support updated
AXI4-Stream Clock Converter (1.1)
 * Version 1.1 (Rev. 5)
 * Architecture support updated
AXI4-Stream Combiner (1.1)
 * Version 1.1 (Rev. 3)
 * Architecture support updated
AXI4-Stream Data FIFO (1.1)
 * Version 1.1 (Rev. 5)
 * Architecture support updated
AXI4-Stream Data Width Converter (1.1)
 * Version 1.1 (Rev. 3)
 * Architecture support updated
AXI4-Stream Interconnect (2.1)
 * Version 1.1
 * Architecture support updated
AXI4-Stream Protocol Checker (1.1)
 * Version 1.1 (Rev. 4)
 * Architecture support updated
AXI4-Stream Register Slice (1.1)
 * Version 1.1 (Rev. 4)
 * Architecture support updated
AXI4-Stream Subset Converter (1.1)
 * Version 1.1 (Rev. 4)
 * Architecture support updated
AXI4-Stream Switch (1.1)
 * Version 1.1 (Rev. 4)
 * Architecture support updated
AXI4-Stream to Video Out (3.0)
 * Version 3.0 (Rev. 6)
 * Added Automative Grade Artix7 support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Accumulator (12.0)
 * Version 12.0 (Rev. 5)
 * Internal GUI update, no functional changes.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Adder/Subtracter (12.0)
 * Version 12.0 (Rev. 5)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface clk_intf
Aurora 64B66B (9.3)
 * Version 9.3 (Rev. 1)
 * Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI, XC7K480TI, XC7Z030I, XC7Z035, XC7Z035I, XC7Z045I, XC7Z100I devices
 * Minor update to XDC for board support
Aurora 8B10B (10.3)
 * Version 10.3 (Rev. 1)
 * Added support for new XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices
 * Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices
 * Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices
 * BUFG added to DRP Clock input
 * Line rate range for -2L speed grade 1.0V Artix devices updated to 6.25Gbps
 * Location constraint changed for Xilinx Evaluation platform boards
Binary Counter (12.0)
 * Version 12.0 (Rev. 5)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Internal GUI updates, no functional changes.
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Block Memory Generator (8.2)
 * Version 8.2 (Rev. 3)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Added support for 7 series Automotive (XA) and Defense Grade (XQ) devices
 * Internal device family change, no functional changes
CIC Compiler (4.0)
 * Version 4.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
CORDIC (6.0)
 * Version 6.0 (Rev. 6)
 * C model correction to match HDL for out of range input values.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
CPRI (8.3)
 * Version 8.3 (Rev. 1)
 * Added support for new defense grade and aero parts.
 * cdc_fifo write address while in reset changed to remove memory collision errors.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Chroma Resampler (4.0)
 * Version 4.0 (Rev. 5)
 * XA Artix-7 (Automotive) Production support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Clocking Wizard (5.1)
 * Version 5.1 (Rev. 5)
 * Internal device family change, no functional changes
 * updates related to the source selection based on board interface for zed board
 
Color Correction Matrix (6.0)
 * Version 6.0 (Rev. 6)
 * Added Automotive Grade Artix7 support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Color Filter Array Interpolation (7.0)
 * Version 7.0 (Rev. 5)
 * XA Artix-7 (Automotive) Production support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Complex Multiplier (6.0)
 * Version 6.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Convolution Encoder (9.0)
 * Version 9.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
DDS Compiler (6.0)
 * Version 6.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
DSP48 Macro (3.0)
 * Version 3.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
DUC/DDC Compiler (3.0)
 * Version 3.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Discrete Fourier Transform (4.0)
 * Version 4.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
DisplayPort (5.0)
 * Version 5.0 (Rev. 1)
 * Added Automotive and new device support in 7 series
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Distributed Memory Generator (8.0)
 * Version 8.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Internal device family change, no functional changes
Divider Generator (5.1)
 * Version 5.1 (Rev. 5)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
 
ECC (2.0)
 * Version 2.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Internal device family change, no functional changes
Ethernet 1000BASE-X PCS/PMA or SGMII (14.3)
 * Version 14.3 (Rev. 1)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Added support for 7-Series Defense-grade, Automotive, and Low Voltage parts.
 * Corrected value of dont_reset_on_data_error input to 7-Series Transceiver FSMs to 0.
 * Changed default value of RXPRBS_ERR_LOOPBACK to 0 for 7-Series Transceivers.
 * Disabling Reset of GT FSMs in case of prbs selection for 7-Series Transceivers.
Ethernet PHY MII to Reduced MII (2.0)
 * Version 2.0 (Rev. 6)
 * No changes
FIFO Generator (12.0)
 * Version 12.0 (Rev. 3)
 * Reduced DRC warnings.
 * Internal device family change, no functional changes
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
FIR Compiler (7.2)
 * Version 7.2 (Rev. 1)
 * Fix for UltraScale Halfband Interpolation optimization with Convergent Rounding and multiple parallel paths.
 * C Model maximum data and coefficient widths updated for UltraScale.
 * Correction to GUI latency calculation.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Add 1 x fs Advanced Channel Sequence to sequence length 24.
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Fast Fourier Transform (9.0)
 * Version 9.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Fixed Interval Timer (2.0)
 * Version 2.0 (Rev. 4)
 * No changes
Floating-point (7.0)
 * Version 7.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
G.709 FEC Encoder/Decoder (2.1)
 * Version 2.1 (Rev. 4)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
 * Version 1.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
 * Version 2.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Gamma Correction (7.0)
 * Version 7.0 (Rev. 6)
 * Added new device family Aartix7 for automotive
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Gmii to Rgmii (3.0)
 * Version 3.0 (Rev. 4)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
High Speed SelectIO Wizard (1.1)
 * Version 1.1 (Rev. 1)
 * Tb updates to correct the example instantiation
 * TX_OUTPUT_PHASE_90 is mapped to RTL
 
IBERT 7 Series GTH (3.0)
 * Version 3.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
IBERT 7 Series GTP (3.0)
 * Version 3.0 (Rev. 7)
 * Added new device support for low power speed grades
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
IBERT 7 Series GTX (3.0)
 * Version 3.0 (Rev. 7)
 * Added Device Support for Software Virtual Devices xc7z035* and low power speed grade -2LI.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
IBERT 7 Series GTZ (3.1)
 * Version 3.1 (Rev. 5)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
IBERT UltraScale GTH (1.1)
 * Version 1.1 (Rev. 1)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 
IBERT UltraScale GTY (1.0)
 * Version 1.0 (Rev. 1)
 * Added new parameter C_USE_MDM.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
ILA (Integrated Logic Analyzer) (5.0)
 * Version 5.0 (Rev. 1)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
IOModule (3.0)
 * Version 3.0
 * No changes
Image Enhancement (8.0)
 * Version 8.0 (Rev. 6)
 * XA Artix-7 (Automotive) Production support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Interlaken (1.4)
 * Version 1.4
 * Different Lane rates with all number of lane combinations from 2 to 12
 * Error Injection test case addition
 * Support for XCVU160 and XCVU190 devices
 * Added core_drp_reset port
Interleaver/De-interleaver (8.0)
 * Version 8.0 (Rev. 5)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
JESD204 (6.0)
 * Version 6.0 (Rev. 1)
 * Added support for Defense-grade Virtex-7Q, Kintex-7Q, Zynq-7000 and Artix-7Q devices
 * Added support for XA Artix-7 and Zynq-7000 devices
 * Enabled all transceiver reference clock values
 * Added multicycle path constraint to AXI path for transmitter cores
 * Fixed an issue with rx_tvalid going high during the ILA sequence. This was caused by Rx buffer output not being reset when the core lost and regained SYNC without a reset being applied.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
JESD204 PHY (1.0)
 * Version 1.0 (Rev. 1)
 * Added support for Defense-grade Virtex-7Q, Kintex-7Q, Zynq-7000 and Artix-7Q devices
 * Added support for XA Artix-7 and Zynq-7000 devices
 * Added missing 7-Series transceiver debug ports to GUI symbol (gtN_rxstatus_out, gtN_rxbyteisaligned_out, gtN_rxbyterealign_out, gtN_rxbufreset_in)
 * Enabled all transceiver reference clock values
JTAG to AXI Master (1.0)
 * Version 1.0 (Rev. 5)
 * Updated constraints across CDC paths between xsdb_clk and axi_aclk
 * Updated wlast deassertion logic after bvalid assertion
 * Updated logic to limit burst length to 16 when AXI4 burst type is FIXED or WRAP
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 
LMB BRAM Controller (4.0)
 * Version 4.0 (Rev. 5)
 * No changes
LTE DL Channel Encoder (3.0)
 * Version 3.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
LTE Fast Fourier Transform (2.0)
 * Version 2.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
LTE PUCCH Receiver (2.0)
 * Version 2.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
LTE RACH Detector (2.0)
 * Version 2.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface clk_intf
LTE UL Channel Decoder (4.0)
 * Version 4.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Local Memory Bus (LMB) 1.0 (3.0)
 * Version 3.0 (Rev. 5)
 * Added bus interface definition for SYS_Rst, no functional changes
Mailbox (2.1)
 * Version 2.1 (Rev. 2)
 * No changes
Memory Interface Generator (MIG 7 Series) (2.3)
 * Version 2.3
 * Updated maximum frequencies and controller rates as per specifications listed in 7 Series and Zync DC and Switching Characteristics Datasheets
 * DDR3 write calibration changes
Memory Interface Generator (MIG) (6.1)
 * Version 6.1
 * Added PHY Only support for DDR3/4
 * AXI Lite support for DDR3/4
 * ECC support for 72 bit DDR3 and DDR4
 * Added support of BL2 and 2x36 bit design for RLDRAM3
 * Added support of DDR4 dual rank UDIMM part MTA18ASF1G72AZ-2G1A1
 * Resolved hold violations on riu_clk
 * Added ability for reset_n to be allocated in a non-memory interface I/O bank.
MicroBlaze (9.4)
 * Version 9.4 (Rev. 1)
 * Added parameters to control synchronization primitives, no functional changes
 * Removed warnings for Block RAM instantiations, no functional changes
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
MicroBlaze Debug Module (MDM) (3.2)
 * Version 3.2 (Rev. 1)
 * Improvements of reset handling, no functional changes
MicroBlaze MCS (2.2)
 * Version 2.2 (Rev. 3)
 * Updated generated BMM files for dual memory ranges
Multiplier (12.0)
 * Version 12.0 (Rev. 6)
 * Disable symmetric rounding checkbox on the GUI when rounding is not supported
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Internal GUI updates, no functional changes.
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Multiply Adder (3.0)
 * Version 3.0 (Rev. 5)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Mutex (2.1)
 * Version 2.1 (Rev. 2)
 * No changes
Peak Cancellation Crest Factor Reduction (5.0)
 * Version 5.0 (Rev. 4)
 * Drives zero upon hardware time out
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interfaces
Processor System Reset (5.0)
 * Version 5.0 (Rev. 6)
 * No changes
QSGMII (3.2)
 * Version 3.2 (Rev. 3)
 * Adding support for XC7Z035 and XC7A15T devices.
 * Adding support for XA/XQ device variants.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Reset of GT FSMs in case of Data Error
RAM-based Shift Register (12.0)
 * Version 12.0 (Rev. 5)
 * Internal GUI update, no functional changes.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
RGB to YCrCb Color-Space Converter (7.1)
 * Version 7.1 (Rev. 4)
 * Added new device family Aartix7 for Automotive
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
RXAUI (4.2)
 * Version 4.2 (Rev. 3)
 * Added support for 7-Series Defense-grade, Automotive, and Low Voltage parts
 * Corrected the filename of the VHDL example design demonstration testbench from EntityName.vhd to example_design_testbench.vhd
 * Added a clock domain crossing synchronizer to signal_detect
 * Tidied up whitespace in HDL files for better alignment and indent consistency
 * When the transceiver Rx PRBS functionality is enabled through the optional transceiver control and status ports, periodic transceiver RX resets are inhibited
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Reducing the default transceiver DRPCLK frequency in the cores out-of-context XDC file from 200MHz to 125MHz.  This is the default frequency used when the core is synthesized in isolation, and is overridden when the core is implemented in a full design.
Reed-Solomon Decoder (9.0)
 * Version 9.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
Reed-Solomon Encoder (9.0)
 * Version 9.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
S/PDIF (2.0)
 * Version 2.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * AXI register interface ready signal generation updated as per axi_lite_ipif update.
SMPTE 2022-1/2 Video over IP Receiver (2.0)
 * Version 2.0 (Rev. 1)
 * Added Automotive and Military Grade device support for 7 series and Zynq
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
SMPTE 2022-1/2 Video over IP Transmitter (2.0)
 * Version 2.0 (Rev. 1)
 * Added Automotive and Military Grade device support for 7 series and Zynq
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
SMPTE SD/HD/3G-SDI (3.0)
 * Version 3.0 (Rev. 3)
 * Added Automotive and Military Grade device support for 7 series and Zynq
SMPTE2022-5/6 Video over IP Receiver (4.0)
 * Version 4.0 (Rev. 1)
 * XA Zynq (Automotive) production support
 * Virtex-7, Kintex-7 and Zynq (Military) production support
 * Fixed memory collision error in bitmap ram
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
SMPTE2022-5/6 Video over IP Transmitter (4.0)
 * Version 4.0 (Rev. 1)
 * XA Zynq (Automotive) production support
 * Virtex-7, Kintex-7 and Zynq (Military) production support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Fixed primary MAC address field stuck at 0 in Ethernet packet
SPI-4.2 (13.0)
 * Version 13.0 (Rev. 6)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
SelectIO Interface Wizard (5.1)
 * Version 5.1 (Rev. 4)
 * Internal device family change, no functional changes
 
Serial RapidIO Gen2 (3.2)
 * Version 3.2 (Rev. 1)
 * Added XA and XQ device support
 * Fixed functional issues around error injection and packet cancellation
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Soft Error Mitigation (4.1)
 * Version 4.1 (Rev. 3)
 * Added support for xc7a15t, xa7a15t, and xc7z035 devices.
 * Added support for -LI speed grades to all Artix and Zynq 7Z010, 7Z015, 7Z020 Devices
 * Added support for -2LI speed grades to Kintex 7K160T, 7K325T, 7K355T, 7K410T, 7K420T, 7K480T and Zynq 7Z030 to 7Z100 Devices
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
System Cache (3.0)
 * Version 3.0 (Rev. 5)
 * No changes
System Management Wizard (1.1)
 * Version 1.1 (Rev. 1)
 * No changes
 
Ten Gigabit Ethernet MAC (14.0)
 * Version 14.0 (Rev. 1)
 * Updated 32-bit example design transmit FIFO to fix overflow issue
 * Updated pattern generator logic to add CDC synchronizer on enable inputs
 * Added support for automotive parts
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Fixed fault sequence count issue in the 32-bit datatpath RS state machine
 * Added missing XDC constraint on the 32-bit datapath MDIO signal inputs to ease timing closure
Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) (5.0)
 * Version 5.0 (Rev. 1)
 * Use the GT Slip functionality to align Autonegotiation frames - no functional change
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Fixed internal core cross clock domain constraints between dclk and the core clock to ease timing closure
Test Pattern Generator (6.0)
 * Version 6.0 (Rev. 3)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * XA Artix-7 (Automotive) Production support
Timer Sync 1588 (1.2)
 * Version 1.2 (Rev. 2)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Tri Mode Ethernet MAC (8.3)
 * Version 8.3 (Rev. 1)
 * Supported 7-series Automotive and Defense-grade parts moved to production status
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
UltraScale FPGAs Transceivers Wizard (1.4)
 * Version 1.4 (Rev. 1)
 * Improved performance of GTH and GTY transceivers via parameter updates
 * Added support for GTH transceiver production-level simulation and device models, and corresponding support for GTH programmable divider values 80 and 100
 * Fixed a bug that prevented activity on the RXRECCLKOUT port if the RXOUTCLK source is not RXPROGDIVCLK
UltraScale FPGA Gen3 Integrated Block for PCI Express (3.1)
 * Version 3.1 (Rev. 1)
 * Enabled Tandem PROM and Tandem PCIe support for xcku060 device.
 * Enabled Partial Reconfiguration over PCIe for xcku040, xcku060, and xcvu095.
 * Removed uncontain clock routing constraints for Tandem Configurations. This is now done in SW.
 * Added support for a2104, b2104, c2104, ffvb1760 and flga2577 packages
VIO (Virtual Input/Output) (3.0)
 * Version 3.0 (Rev. 5)
 * Internal device family change, no functional changes
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 
Video Deinterlacer (4.0)
 * Version 4.0 (Rev. 7)
 * XA Artix-7 (Automotive) production support
 * XA Artix-7, Virtex-7, Kintex-7 and Zynq (Military) production support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Video In to AXI4-Stream (3.0)
 * Version 3.0 (Rev. 6)
 * Added Automotive Grade Artix7 support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Video On Screen Display (6.0)
 * Version 6.0 (Rev. 7)
 * Added Automotive Grade Artix7 support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Video Scaler (8.1)
 * Version 8.1 (Rev. 4)
 * XA Artix-7 (Automotive) Production support
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
Video Timing Controller (6.1)
 * Version 6.1 (Rev. 4)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * XA Artix-7 (Automotive) Production support
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (3.0)
 * Version 3.0 (Rev. 4)
 * Added synthesis support for External PIPE Interface mode
 * Enhancement to allow debug cores to work better within Tandem designs. Build_stage1.tcl now runs before place_design and handles bscan primitives.
 * Changed the pipe mode simulation options in GUI to radio buttons (No change in the functionality)
 * Added interface for powerdown ports which is enabled when Enable Powerdown Interface option on basic page in Advanced mode is selected
Viterbi Decoder (9.1)
 * Version 9.1 (Rev. 1)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
XADC Wizard (3.0)
 * Version 3.0 (Rev. 6)
 * Internal device family change, no functional changes
 
XAUI (12.1)
 * Version 12.1 (Rev. 4)
 * Added support for 7-Series Defense-grade, Automotive, and Low Voltage parts
 * Edited the example design demonstration testbench to monitor the mgt_tx_ready signal before beginning MDIO accesses (previously the testbench waited for a fixed duration which was sometimes overly conservative)
 * Added a clock domain crossing synchronizer to signal_detect.
 * Tidied up whitespace in HDL files for better alignment and indent consistency
 * When the transceiver Rx PRBS functionality is enabled through the optional transceiver control and status ports, periodic transceiver RX resets are inhibited
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Reducing the default transceiver DRPCLK frequency in the cores out-of-context XDC file from 200MHz to 125MHz.  This is the default frequency used when the core is synthesized in isolation, and is overridden when the core is implemented in a full design.
YCrCb to RGB Color-Space Converter (7.1)
 * Version 7.1 (Rev. 4)
 * Added new device family Aartix7 for Automotive
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
ZYNQ7 Processing System (5.5)
 * Version 5.5
 * No changes
 
ZYNQ7 Processing System BFM (2.0)
 * Version 2.0 (Rev. 3)
 * No changes
axi_sg (4.1)
 * Version 4.1
 * No changes
interrupt_controller (3.1)
 * Version 3.1
 * No changes
lib_bmg (1.0)
 * Version 1.0
 * No changes
lib_cdc (1.0)
 * Version 1.0
 * No changes
lib_fifo (1.0)
 * Version 1.0
 * No changes
lib_pkg (1.0)
 * Version 1.0
 * No changes
lib_srl_fifo (1.0)
 * Version 1.0
 * No changes
 
AR# 62882
Date Created 11/19/2014
Last Updated 12/02/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4