We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62885

2014.4 - Vivado IP Integrator - Can I package my MicroBlaze BD design and add this to another BD design


I have a MicroBlaze Block Design (BD) that I want to package up, and add to a separate BD design.

Is this possible?


The Vivado tools do not yet support the Association of ELF files to packaged designs. 

To work around this, follow the steps below:

Step 1: 

Creating the Packaged IP design files.

Before packaging the MicroBlaze BD, you will need to do the following:

  • Generate the Output Products
  • Synthesize the Design
  • write_bmm
  • Export to SDK to create the HDF file

Step 2: 

Create the new block design containing the newly created packaged MicroBlaze BD.

Step 3:

Run Synthesis and open the synthesized design.

Step 4: 

Create the ELF files

  • Launch SDK
  • Select File -> BSP
    You will be prompted to add the Hardware platform file.
    Use the HDF file created in Step 1.
  • Create the Application.
  • Exit SDK.

Step 5: 

Add the ELF and BMM files.

Step 6:

Modify the BMM file to make it relevant to the new project structure.

Below is an example of a BMM file. 

In the section highlighted in red, the hierarchy is removed. 

In the section highlighted in green, the ADDRESS_MAP is changed to make the BMM file specific to each packaged MicroBlaze BD:


The Hierarchy can be obtained from the netlist. 

In the below example I have two packaged MicroBlaze BD's added to my block design:


Step 7:

Set the source file properties to associate the ELF.

The SCOPED_TO_CELLS, and SCOPED_TO_REF (Referred to as STC, and STR respectively in this Answer Record) for the BMM and ELF files need to be set. 

The STC points to the processor cell, and the STR points to the module that contains the STC. The STC is not needed for the BMM file.

To obtain this, open the netlist. 

Below is an example that highlights the STC and STR for each packaged MicroBlaze BD file in red and green respectively:


 In the example above, the STR and STC for the ELF files for each packaged MicroBlaze BD files are:

  • STC for mb_design_0 is microblaze_0
  • STC for mb_design_1 is microblaze_0
  • STR for mb_design_0 is mb_design__xdcDup__1
  • STR for mb_design_1 is mb_design

The STR, and STC for the BMM files for each packaged MicroBlaze BD file are:

  • STR for mb_design_0 is mb_design__xdcDup__1
  • STR for mb_design_1 is mb_design


To set the property for each source file (ELF and BMM), highlight the file in sources, then in the source file properties search for the SCOPED_TO_CELLS, and SCOPED_TO_REF.

Enter the properties here.

Step 8: 

Verify that the BRAM contents are updated.

Close, and re-open the synthesized design.

In the re-open synthesized design, Type CTRL+F and search for the BRAM for PRIMITIVE_TYPE.

Under the list of BRAMs, select any of the BRAMs and in the cell properties, scroll to the INIT_XX properties. 

You should see the memories populated.

Note: if you see any warning related to the Memdata, or BMM_INFO when you re-open the synthesis design, then the issues is related to the STR and STC not being set correctly.

AR# 62885
Date Created 11/19/2014
Last Updated 12/09/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3