UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62888

2014.3 Vivado Placement - False Place 30-143 errors on xc7a200tiffg1156-1L device

Description

A case has been seen where a false Place 30-143 error was reported for the xc7a200tiffg1156-1L device:

[Place 30-143] Sub-optimal placement for an IBUFDS / GT component pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gtwizard_0_support_i/gt_usrclk_source/Q0_CLK0_GTREFCLK_OUT] >

gtwizard_0_support_i/gt_usrclk_source/ibufds_instQ0_CLK0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y2
gtwizard_0_support_i/common0_i/gtpe2_common

Solution

This placement bug is scheduled to be fixed for the 2015.1 release.

In the meantime, if the message is confirmed to be incorrect, it can be overridden using the CLOCK_DEDICATED_ROUTE constraint provided in the message text.
AR# 62888
Date Created 11/19/2014
Last Updated 11/20/2014
Status Active
Type General Article
Devices
  • Artix-7
Tools
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3