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AR# 62891

MIG 7 Series - DDR3 - 72-bit AXI4 interface generated with ECC disabled

Description

Version Found: MIG v2.2
Version Resolved: See (Xilinx Answer 54025)

There is a known issue in MIG v2.2 where a 72-bit DDR3 AXI interface will be incorrectly generated with ECC disabled, even though ECC is shown enabled in the GUI.  

For 72-bit AXI interfaces, ECC is required as noted in (UG586):

eccmask.PNG




Solution

To work around this issue, the following parameters will need to be modified in the <core_name>_mig.v module:
 

   parameter ECC                   = "ON",           // previously "OFF"
   parameter DATA_WIDTH            = 64,       // previously 72

Revision History:
01/26/2015 - Initial Release

AR# 62891
Date Created 11/19/2014
Last Updated 03/05/2015
Status Active
Type Known Issues
IP
  • MIG 7 Series