During an Implementation run, the following crash is seen in opt_design:
This issue has been fixed for Vivado 2015.1 which is scheduled for release in April, 2015.
Until then, one of the following methods can be used as a work-around:
The parameter below can be set before "opt_design".
set_param pwropt.cacheClockInfoForPowerOpt false
This disables caching of the clock information during the block RAM power optimization stage.
However, this can potentially increase the block RAM power optimization runtime.
In a scripted non-project flow, create a post-synthesis dcp.
Close the design with "close_design", then load the check point with "open_checkpoint post_synth.dcp" before running "opt_design".
The parameter below can be used:
set_param logicopt.enablePowerLopt false
This disables the block RAM power optimization.