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AR# 62912

LogiCORE PLBV46 AXI Bridge does not return out of order AXI error conditions correctly.

Description

If a primary and secondary read are initiated from the PLB and the AXI response is out of order, either a DECERR or SLVERR occurs on the AXI bus for the secondary read.  

This secondary read is returned first and gets saved in the read FIFO. 

The error does not get logged.

 

Also, there is a documentation error in (DS711):

In Table 9: SESR
 
bits 0-20 should be bits 0-19
bits 21-23 should be bits 20-23     <- the PLB Size is a 4 bit value. The VHDL uses 4 bits.

Solution

To work around this issue, edit the axi_master_burst_rd_thrds.vhd:

-------------------------------------------------------------------------------
-- AXI secondary read response combo for error registers
-- This combinatorial process assigns the secondary read response from AXI
-- which is needed to update the error registers.
-------------------------------------------------------------------------------
 
           SEND_SCNDRY_SPLB_RD_RESP_COMBO : process(plb_issue_rd_ack_sa_sm,
                                              rcvd_sa_data_first, --  added
                                                    M_AXI_RRESP_i ) is
           begin
               if ((plb_issue_rd_ack_sa_sm = '1') or
   (rcvd_sa_data_first     = '1')) then -- added
                   Err_scndry_rd_resp  <= M_AXI_RRESP_i;
               else
                   Err_scndry_rd_resp  <= "00";
 
               end if;
           end process SEND_SCNDRY_SPLB_RD_RESP_COMBO;


There are no plans to fix these issues.

AR# 62912
Date Created 11/21/2014
Last Updated 03/25/2015
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE
IP
  • Interconnect Infrastructure