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AR# 62957

2014.3 OTN IP simulations producing ERROR: (vcom-1129) Type mismatch for generic "IS_CLKRSVD0_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".

Description

When simulating the OTN 100G/40G/10G PI PHY IP simulations, the following errors associated with the GTHE2_CHANNEL or GTXE2_CHANNEL can be encountered:

** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_CLKRSVD0_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_CLKRSVD1_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_CPLLLOCKDETCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_DMONITORCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_DRPCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_GTGREFCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_RXUSRCLK2_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_RXUSRCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_SIGVALIDCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_TXPHDLYTSTCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_TXUSRCLK2_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".
** Error: U:/HEAD/ip/10g_pi_phy/dev/hw/sim/Test_Cases/TC_001_OTU2_Transparent.vhd(247): (vcom-1129) Type mismatch for generic "IS_TXUSRCLK_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".



How can I work around these errors in simulation?

Solution

This is a known issue in Vivado 2014.3 with the latest versions of these IPs.

The affected IP are:


  • V7 GTH PI PHY100            (EF-DI-V7-GTH-PI-PHY100-PROJ)
  • V7 GTH PI PHY10              (EF-DI-V7-GTH-PI-PHY10-PROJ)

To workaround/avoid this issue it is necessary to install the attached patch into the 2014.3 installation prior to compiling your QuestaSim/ModelSim libraries.

Patch Content:


In addition to this readme (patch_readme/AR62975_OTNIP_2014.3_preliminary_rev1_readme.txt), the AR62975_OTNIP_2014.3_preliminary_rev1.zip file contains the following files and directories:
 
   Critical file(s) driving the patch:

  • data\vhdl\src\unifast\secureip\GTHE2_CHANNEL.vhd
  • data\vhdl\src\unifast\secureip\GTXE2_CHANNEL.vhd


Installation/Use:

Unzip the patch directly into your Vivado Installation by following the steps below:

  1. Copy the Zip file to %XILINX_VIVADO% location, (for example C:\tools\Xilinx\Vivado\2014.3\)
  2. Extract the contents of the ".zip" archive directly to this location.
  3. This will overwrite the files mentioned above in your local install. (You may wish to move the originals prior to extracting this archive)
  4. Recompile your Xilinx libraries to ensure the updated files have been compiled into the SecureIP compiled library.


Attachments

Associated Attachments

Name File Size File Type
AR62975_OTNIP_2014.3_preliminary_rev1.zip 49 KB ZIP
AR# 62957
Date Created 11/26/2014
Last Updated 11/28/2014
Status Active
Type General Article
Devices
  • Virtex-7
  • Artix-7
  • Kintex-7
  • Zynq-7000
Tools
  • Vivado Design Suite - 2014.3