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AR# 63051

Vivado 2014.4 AXI Interconnect - [BD 41-237] Bus Interface property READ_​WRITE_​MODE does not match between /​axi_​clock_​converter_​5/​S_​AXI(WRITE_​ONLY) and /​axi_​interconnect_​0/​xbar/​M01_​AXI(READ_​WRITE)


When using a read-only or write-only peripheral connected to an AXI Interconnect in Vivado IP Integrator, the following Critical Warning occurs:

[BD 41-237] Bus Interface property READ_WRITE_MODE does not match between /axi_clock_converter_5/S_AXI(WRITE_ONLY) and /axi_interconnect_0/xbar/M01_AXI(READ_WRITE)

What should I do about this warning?


This warning can generally be ignored or suppressed.

It is created due to a limitation in how the AXI Interconnect individual interfaces are modeled.

To work around the issue:

  • Ignore the Critical Warning, potentially using the message suppression feature.
    Note: All messages about mismatching bus interface properties will also be suppressed.
  • Repackage the custom slave as a read/write slave, even if it does not have logic for both directions.
    There is currently no protection from a bidirectional master accessing the unsupported direction of a unidirectional slave.
    Note: There will be slightly more logic utilization in the AXI Interconnect with this option.

A fix for this behavior is being explored for Vivado 2015.1.

AR# 63051
Date 02/13/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.2
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  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
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  • AXI Interconnect
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