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AR# 63065

2014.4 Vivado IP Flows - Generating IP using Tcl commands creates '_funcsim.vhdl/.v' files in incorrect language


In Vivado 2014.4 I generate an IP core using the Tcl command flow. 

The *_funcsim.vhd file is written in Verilog and *_funcsim.v is written in VHDL.

I am creating an IP core with the following commands:
  1. create_ip -name axi_interconnect -vendor xilinx.com -library ip -module_name axi_interconnect -dir .
  2. generate_target all [get_files ./axi_interconnect/axi_interconnect.xci]
  3. synth_ip [get_files ./axi_interconnect/axi_interconnect.xci]

When I check the generated 'funcsim' files, I see the following.

The 'axi_interconnect_0_funcsim.vhdl' contains verilog code. This can be seen in files the and wrong command is seen in the header.  e.g. 'write_verilog'
The 'axi_interconnect_0_funcsim.v' contains vhdl code.  This can be seen in files the and wrong command is seen in the header. e.g. 'write_vhdl'


The files are correct but have the incorrect file extension.

To work around this issue, change the file extension to the correct value.

AR# 63065
Date Created 12/09/2014
Last Updated 01/09/2015
Status Active
Type Known Issues
  • Vivado Design Suite