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AR# 63077

AXI Bridge for PCI Express Gen3 v1.0 (Rev1) - s_axis_arready is not asserted by default

Description

The AXI Bridge for PCI Express Gen3 v1.0 core does not assert an s_axis_arready signal by default.

Solution

This issue occurs because the core does not have the Bus Master Enable (BME) bit set in the Command Register by default.
 
The BME bit must be set to initiate Memory Read operations (for s_axis_arready to be asserted) towards the upstream device (towards Root Complex).

In simulation, this bit can be set with the configuration write task below in pci_exp_usrapp_tx.v, in the example design.
 

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h04, 32'h00000007, 4'h1)


Revision History:
10/12/2014 - Initial Release


AR# 63077
Date Created 12/10/2014
Last Updated 02/16/2015
Status Active
Type General Article
IP
  • AXI PCIe Gen3