This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.4 Rev1 released with the Vivado 2014.4 design tool.
Issue 1: Example design running into timeout with low line rate for Artix 7 GTP.
Increase time_out_2ms to 6.5ms in the RX startup FSM code.
This is required because rxpmaresetdone is taking a long time to bring the required negedge out.
The Following code snippet shows this update.
Issue 2: RXCDR_CFG is incorrect for certain configurations in GTX.
Please change the RXCDR_CFG for RXOUTDIV= 4 and 8.
The Wizard sets it incorrectly.
Please follow (UG476) Table 4-17
Issue 4: Revision update is not shown in the IP catalog for gtwizard_v3_4
The Wizard has been updated in 2014.4 and the revision has been changed to 1.
However, due to issues in the coreinfo.yml file the revision update is not seen in IP Catalog: