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AR# 63096

7 Series FPGAs Transceiver Wizard v3.4 Rev1 - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.4 Rev1 released with the Vivado 2014.4 design tool.


Issue 1: Example design running into timeout with low line rate for Artix 7 GTP.


Increase  time_out_2ms to 6.5ms in the RX startup FSM code.

This is required because rxpmaresetdone is taking a long time to bring the required negedge out.

The Following code snippet shows this update.

localparam integer WAIT_TIMEOUT_2ms   = 6500000 / STABLE_CLOCK_PERIOD;  //6.5 ms time-out rxpmaresetdone is taking a long time to bring the required negedge out

Issue 2:  RXCDR_CFG is incorrect for certain configurations in GTX.


Please change the RXCDR_CFG for RXOUTDIV= 4 and 8. 

The Wizard sets it incorrectly.

Please follow (UG476) Table 4-17  


Issue 3:  DFE is incorrectly set to HOLD after adaptation for GTH.

Please refer to (Xilinx Answer 63110) for details and workaround.

Issue 4: Revision update is not shown in the IP catalog for gtwizard_v3_4


The Wizard has been updated in 2014.4 and the revision has been changed to 1. 

However, due to issues in the coreinfo.yml file the revision update is not seen in IP Catalog:

However, the change log has been updated with the latest revision:

Issue 5:
Update to GTZ reset sequence implementation.
Please refer to (Xilinx Answer 63590) for details and work around.

Revision History:
02/23/2015 - Added Issue 5
01/27/2015 - Added Issue 4
01/13/2015 - Added Issue 3
12/15/2014 - Initial Release
AR# 63096
Date Created 12/11/2014
Last Updated 02/25/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2014.4
  • 7 Series FPGAs Transceivers Wizard