When determining the pinout for an UltraScale design using Tandem Configuration, specific requirements regarding transceiver banks must be considered.
Which PCIe blocks, GT quads and GTs can be used with Tandem PCIe or Tandem PROM?
What considerations must be understood when designing with these cores?
In most cases, the location is in the lower right corner of the die.
The exceptions are the three largest Virtex UltraScale devices, which are comprised of three Super Logic Regions (SLR).
The locations for these three are the lower right corner of the central SLR.
If a Lane Width of X8 is selected, two entire GT quads are consumed.
These quads are the two closest to the aforementioned PCIe block.
The stage one pblock for the Tandem IP will automatically select these two quads.For widths of X4 and smaller, there are choices that can be made.
When selecting the upper quad (for example, quad 225 in the KU060), the lower quad cannot be used for other GTs in the design, as it is included in the stage 1 pblock.
due to the fact that the stage 1 region must be reserved for exclusive use of
stage 1 logic and routing this allows the stage 1 bitstream to be preserved
when Field Updates (multiple stage 2 bitstreams) are required.
The stage 1 pblock illustrates this, shown here in the example design created with the IP.
Within a quad, the default GT locations selected for X1 or X2 modes are the upper-most GTs, as documented in Appendix B of (PG156).
These locations can be modified by constraining the GT_CHANNEL instances to other XY coordinates within the quad chosen during IP creation.
Figures 3 and 4 show a Gen1x1 configuration with a non-default GT location selected.
Finally, within the quads selected for stage 1, whether it be a single (lower) quad or both, any GTs not used for the PCIe IP cannot be used for the user design in stage 2.