UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63123

2014.4 Partial Reconfiguration - After the Reconfigurable Module is updated to black-box, pr_verify fails on a clock net of the reconfigurable module

Description

After completing route_design with the reconfigurable module, I export a checkpoint, named full_routed_RM1.dcp.

Then I update the reconfigurable module to blackbox and export another checkpoint, named full_RM1_black_box.dcp.

When I run the pr_verify command for the above 2 dcp files, I get the following error for a clock pin of the reconfigurable module.

Example command:
pr_verify ./full_RM1_black_box.dcp ./full_routed_RM1.dcp

Error Message:
 

ERROR: [Constraints 18-892] HDPRVerify-09: Mismatched Partition-Pin-Location found.
There is a difference at interface net n_0_clk_IBUF_inst_BUFG connected to pin can0./n_0_clk_IBUF_inst_BUFG.
Both design check points must have the same location for the equivalent Partition-Pins.

Solution

This issue is fixed in the 2015.1 release of Vivado Design Suite.

AR# 63123
Date Created 12/14/2014
Last Updated 02/19/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
Tools
  • Vivado Design Suite - 2014.4