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AR# 63125

2014.3 Partial Reconfiguration - Design getting DRC error on missing LOC in the 2nd configuration


In my Partial Reconfiguration (PR) design, the I/O are constrained in the first configuration. 

No DRC issues are found.

However, in the second configuration, when static place/route results are imported, a DRC issue is found relating to missing I/O constraints:

UCIO-1#1 Critical Warning
Unconstrained Logical Port 
16 out of 54 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Linear_Flash_data[15:0].
Related violations: <none>



This DRC for missing LOC constraint can be ignored safely and is removed in the 2015.1 release of Vivado Design Suite.
AR# 63125
Date 02/24/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2014.3