We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63141

2014.4 Partial Reconfiguration - pr_verify fails on GND net if first configuration run is using multiple EDIF/NGC files, but passes if DCP is created first


The static design is made up of several EDIF, NGC and DCP files. 

When I load these netlist files one by one into memory and complete the first configuration run to pr_verify, pr_verify fails on GND nets:

ERROR: [Constraints 18-893] HDPRVerify-10: the net GND (or <const0>) uses routing node CLBLM_R_X255Y326/CLBLM_LOGIC_OUTS11 i n design check point ./impl/post_route_down.dcp, yet this routing node is not used by the same net in design check point ./i mpl/post_route_up.dcp. The routing nodes used to route net GND (or <const0>) must be the same in both design check points

This does not occur if I merge the static netlist files into one DCP, load this DCP into memory and then run the subsequent flow with exactly the same scripts.



This issue is caused by a failure to lock the static GND net correctly.

It is fixed in the 2015.1 release of Vivado.


AR# 63141
Date Created 12/16/2014
Last Updated 03/04/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4