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AR# 63153: 2014.3 Hierarchical Design - HD.CLK_SRC constraint fails to be set on clock bus port
2014.3 Hierarchical Design - HD.CLK_SRC constraint fails to be set on clock bus port
There is a 12 bit clock bus port in my design.
Vivado will not allow a HD.CLK_SRC constraint to be applied to it, even though the clock exists.
I am receiving the Error Message below:
ERROR: [Common 17-69] Command failed: Cannot set clk_src on port Fifo_Rd_Clk that does not contain a clock constraint or it is not a clock net. please use the create_clock constraint to create a clock on this port prior to setting HD.CLK_SRC. I can see clock do existing in the design with the below command: %get_clocks -of [get_ports Fifo_Rd_Clk]
This issue is fixed in the 2015.1 release of Vivado.