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AR# 63164

2014.x Vivado Sysgen - Example M-file fails to work for M-HWCosim over JTAG for Zync design


The example M-file created by System Generator for M-HWCosim over JTAG will not work.
This file is generated by selecting the option "Create Testbench" within the Sysgen token.

Running Hardware Co-Simulation by pressing the simulation button from the MDL works as expected.


This is a known issue and has been fixed in the 2015.1 release.

There are 2 workarounds:

Work-around 1:
Run via the GUI by pressing the simulate button to run Hardware Co-Simulation.
Work-around 2:
Modify the associated *.hwc file in the netlist directory by changing the following line:

'useZynqReconfigScript' => true,


'useZynqReconfigScript' => false,

This will disable launching XMD in M-HWCosim.

If using option 2 above, it is also recommended that the board be power-cycled to reset the PL portion of the SoC to a known state between successive runs.

AR# 63164
Date Created 12/17/2014
Last Updated 02/26/2015
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1