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AR# 63165

MIG 7 Series DDR2/DDR3 v2.3- Additional BUFG added in "opt_design" for the "freq_refclk" can lead to minimum pulse width timing violations

Description

Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)

Opt_design adds a BUFG between the PLL output clock "freq_refclk" and the FREQREFCLK input to the PHASER_IN in the PHY. 

This can cause minimum pulse width violations in the MIG design.


Solution

It can be seen in the implementation log files that the "retarget" phase in "opt_design" has added this BUFG to the PLL output:

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 10 inverter(s) to 78 load pin(s).
INFO: [Opt 31-194] Inserted BUFG ClkFreq_BUFG_inst to drive 22 load(s) on clock net ClkFreq
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
INFO: [Opt 31-49] Retargeted 0 cell(s).

This extra BUFG is not required and should be removed. 

The issue can be worked around with the following options:

1) Avoid running the "retarget" option when running "opt_design"

2) Set the following parameter to disable BUFG insertion.

Do this prior to running "opt_design"
set_param logicopt.enableBUFGinsertCLK 0

3) Modify the MIG core directly to include "DONT_TOUCH" attributes on the clock output signals from the PLL going to the PHASERs:
 

(* dont_touch="true" *) wire        freq_refclk;
(* dont_touch="true" *) wire        mem_refclk;
(* dont_touch="true" *) wire        sync_pulse;


Revision History:
1/21/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 63165
Date Created 12/17/2014
Last Updated 01/26/2015
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
IP
  • MIG