Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)
Opt_design adds a BUFG between the PLL output clock "freq_refclk" and the FREQREFCLK input to the PHASER_IN in the PHY.
This can cause minimum pulse width violations in the MIG design.
It can be seen in the implementation log files that the "retarget" phase in "opt_design" has added this BUFG to the PLL output:
This extra BUFG is not required and should be removed.
The issue can be worked around with the following options:
set_param logicopt.enableBUFGinsertCLK 0
1/21/2015 - Initial Release