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AR# 63168

2014.3 Vivado Partial Reconfiguration - Routing antenna issue occurs after executing "update_design -black_box" for carving Reconfigurable Partition

Description

This is a MIG wrapper design targeted on an UltraScale device. 

The MIG example design is the Reconfigurable Partition itself, with the top/static being the simple wrapper.


The routing for the first configuration completes successfully and report_route_status flags no error in the netlist.


I run the following command to carve out the Reconfigurable Partition:

update_design -black_box -cell example_top_inst

 

However, there are routing errors on the two differential clock inputs: 

c0_sys_clk_n and c0_sys_clk_p.


This can be found using the report_route_status command.

Nets with Routing Errors:
 

c0_sys_clk_n
Unplaced Pin: example_top_inst/c0_sys_clk_n
Antenna and Island Nodes:
HPIO_L_X33Y60/HPIO_DIFF_IBUF_46_PAD_RES_1_PIN
HPIO_L_X33Y60/HPIO_IOB_44_PAD_RES
c0_sys_clk_p
Unplaced Pin: example_top_inst/c0_sys_clk_p
Antenna and Island Nodes:
HPIO_L_X33Y60/HPIO_DIFF_IBUF_46_PAD_RES_0_PIN
HPIO_L_X33Y60/HPIO_IOB_43_PAD_RES

 
These input pins to the Reconfigurable module drive the DIFF_IN_N and DIFF_N_P pins of a DIFFINBUF primitive (implemented on HPIODIFFINBUF site).
 
PR_routing.png




Solution

In this design, the embedded I/O connects to the Reconfigurable Module's port and no PPLOC is assigned as expected.


However, when performing carving, only placed driver/loads are carved away, the routing is still preserved, which causes the routing antenna issue.

This issue is fixed in the 2014.4 release of Vivado.

 

AR# 63168
Date Created 12/17/2014
Last Updated 03/25/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.3