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AR# 63171

7 Series SelectIO wizard, IP Integrator - Variable mode IDELAY clock tied low

Description

When the you add an interface to the Block design using the SelectIO wizard and opt for an IDELAY in variable mode and an IDDR, the clock input of the IDELAY is grounded and not available to the rest of the design. 

 
This behavior is different to an RTL design where the IDELAY clock is an input port to the IP. 
 
When using the Variable IDELAY and the ISERDES, the wizard correctly connects the C input of the IDELAY to CLK_DIV. 
 
 

Solution

When the you add an interface to the Block design using the SelectIO wizard and opt for an IDELAY in variable mode and an IDDR, the clock input of the IDELAY is grounded and not available to the rest of the design. 

 
You can see this when you look into the synthesized netlist. 
selectio_wiz_bd_issue.PNG

 
 
This behavior is not seen in an RTL design where the IDELAY clock is an input port to the IP. 
 
 
To work around this issue you can do the following:
 
1. Create an RTL project.
2. Add in the IP and connect the clock properly in the RTL code. 
3. Package this code up as an IP.
4. This can now be added to the Block Design. 
 
 


AR# 63171
Date Created 12/17/2014
Last Updated 02/23/2015
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2014.4
IP
  • SelectIO Wizard