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AR# 63174

Vivado Constraints - 7 Series - How to constrain the input/output interface of post-configuration User Access to SPI/BPI Flash?

Description

Are there any guidelines for adding timing constraints of a post-configuration user access interface to SPI/BPI Flash?

Below is an example of the interface connection of SPI Flash:






Solution

Below are a set of constraints for a 7 Series SPI example. 

Similar steps can be taken for a BPI interface.

A common use case is to use an MMCM to generate the clock for USERCCLKO of STARTUPE2 component, as demonstrated in the below diagram. 

The following constraints are based on this clock topology.




1. CCLK is a dedicated FPGA pin and it cannot be constrained. 

However, you can create a generated clock on STARTUPE2_inst/USRCCLKO to be used in the input and output delay constraints.

 create_generated_clock -name cclk -source [get_pins STARTUPE2_inst/USRCCLKO] -combinational [get_pins STARTUPE2_inst/USRCCLKO]

The master clock source pin (-source option) could be any pin in the fanin of STARTUPE2_inst/USRCCLKO.
 

2. The set_clock_latency constraints are used to specify the clock latency through the STARTUPE2 primitive and board trace when it arrives at the SPI Flash.

The insertion delay includes the propagation delay from USERCCLKO to CCLK pin and the trace delay on the board.

set_clock_latency -min Tusrcclko_min+trce_cclk_min [get_clocks cclk]<
set_clock_latency -max Tusrcclko_max+trce_cclk_max [get_clocks cclk]          


Tusrcclko_min/Tusrcclko_max: min/max value of Tusrcclko in DC and Characteristics Data Sheet of the 7 series device.
trce_cclk_min/trce_cclk_max : min/max trace delay on CCLK lane on board.
 

3. Input delay constraint for MISO(DIN/D[01]) signal:
 

set_input_delay -clock cclk -max tco_max+trce_dly_max [get_ports inSpiMiso] <-clock_fall>
set_input_delay -clock cclk -min tco_min+trce_dly_min [get_ports inSpiMiso] <-clock_fall>


Use the Vivado XDC Template: XDC -> Timing Constraints -> Input Delay Constraints -> System Synchronous -> (choose according to the data rate and clock edge)
 
tco_max: clock (low) to output valid in SPI Flash Data Sheet
tco_min: output hold time in SPI Flash Data Sheet

4. Output delay constraint for MOSI/D[00] signal:
 

set_output_delay -clock cclk -max trce_dly_max+tsu [get_ports outSpiMosi]
set_output_delay -clock cclk -min trce_dly_min-thd [get_ports outSpiMosi]

Use the Vivado XDC Template: XDC -> Timing Constraints -> Output Delay Constraints -> System Synchronous -> (choose according to the data rate and clock edge)
 
tsu : data in setup time in SPI Flash Data Sheet
thd : data in hold time in SPI Flash Data Sheet

5. Output delay constraint for FCS_B signal:
 

set_output_delay -clock cclk -max trce_dly_max+tsu [get_ports outSpiCsB]
set_output_delay -clock cclk -min trce_dly_min-thd [get_ports outSpiCsB]

Use the Vivado XDC Template: XDC -> Timing Constraints -> Output Delay Constraints -> System Synchronous -> (choose according to the data rate and clock edge)
 
tsu : chip select setup time in SPI Flash Data Sheet
thd : chip select hold time in SPI Flash Data Sheet

Constraint Examples:
 
Below is a set of example constraints based on the "MT25QL512AB" SPI Flash data sheet from MICRON.

In these example constraints, the trace delays on board are assumed to be 0.

create_generated_clock -name cclk -source [get_pins STARTUPE2_inst/USRCCLKO] -combinational [get_pins STARTUPE2_inst/USRCCLKO]
set_clock_latency -min  0.5 [get_clocks cclk]
set_clock_latency -max  6.7 [get_clocks cclk]
set_input_delay -clock cclk -max 6 [get_ports inSpiMiso] -clock_fall
set_input_delay -clock cclk -min 1 [get_ports inSpiMiso] -clock_fall
set_output_delay -clock cclk -max 1.75 [get_ports outSpiMosi]
set_output_delay -clock cclk -min -2.5 [get_ports outSpiMosi]
set_output_delay -clock cclk -max 3.375 [get_ports outSpiCsB]
set_output_delay -clock cclk -min -3.375 [get_ports outSpiCsB]

How are paths analyzed for the interface based on these constraints?
 
This interface looks like it is system synchronous as shown below.

So all paths crossing the interface are analyzed as a clock domain crossing between two synchronous clocks.

See the following two examples:

1. MISO path (input delay)



2. MOSI path (output delay)



AR# 63174
Date Created 12/17/2014
Last Updated 04/07/2015
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite