Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)
When simulating a 2:1 controller, two "X" glitches can be seen on the address and command buses prior to ddr3_reset_n going high.
The issue is specific to 2:1 mode, a 4:1 core with similar settings does have this problem.
01/19/2014 - Initial Release