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AR# 63224

Vivado simulator - Error "[VRFC 10-454] cannot open vhdl file" may occur in Windows OS when running behavioral simulation on IP Example Design


When I run behavioral simulation on the example design of the IP "Ethernet 1000BASE-X PCS/PMA or SGMII", I receive the following error message:

xvhdl -m64 -prj demo_tb_vhdl.prj

Determining compilation order of HDL files.
ERROR: [VRFC 10-454] cannot open vhdl file ../../../gig_ethernet_pcs_pma_0_example.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_v14_3/hdl/gig_ethernet_pcs_pma_v14_3_rfs.vhd
ERROR: [XSIM 43-3317] Sorting of project file "demo_tb_vhdl.prj" failed. Please sort the files manually, add a nosort keyword on the last line of "demo_tb_vhdl.prj" and rerun the compiler.
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '' file for more information.

The issue only occurs in the Windows Operating System.



The error is due to a Windows OS limitation.

Windows has a 260 character limit on the maximum length for a path.

When the IP infrastructure delivers output products in a path whose length exceeds the limit, simulation failure can occur.

To work around the issue, try to reduce the length of the full path name of the simulation file.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58884 Xilinx Simulation Solution Center - Design Assistant - IP Simulation N/A N/A
AR# 63224
Date 04/08/2015
Status Active
Type General Article
  • Vivado Design Suite
  • Ethernet 1000BASE-X PCS/PMA or SGMII
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