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AR# 63228

2013.x,2014.x Vivado - Primitive Instantiation Template for BUFR of 7 series is incorrect

Description

In Vivado versions prior to 2015.1, the below Language Template (Verilog/VHDL) for instantiating the BUFR of 7 series devices is incorrect.

Verilog -> Device Primitive Instantiation -> Artix-7/Kintex-7/Virtex-7 -> Clock Components -> Clock Buffers -> BUFR

   BUFR #(
      .BUFR_DIVIDE("BYPASS"),   // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" 
      .SIM_DEVICE( ""7SERIES"" )  // Must be set to "7SERIES" 
   )
   BUFR_inst (
      .O(O),     // 1-bit output: Clock output port
      .CE(CE),   // 1-bit input: Active high, clock enable (Divided modes only)
      .CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
      .I(I)      // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
   );

VHDL -> Device Primitive Instantiation -> Artix-7/Kintex-7/Virtex-7 -> Clock Components -> Clock Buffers -> BUFR

   BUFR_inst : BUFR
   generic map (
      BUFR_DIVIDE => "BYPASS",   -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" 
      SIM_DEVICE => ""7SERIES""  -- Must be set to "7SERIES" 
   )
   port map (
      O => O,     -- 1-bit output: Clock output port
      CE => CE,   -- 1-bit input: Active high, clock enable (Divided modes only)
      CLR => CLR, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
      I => I      -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
   );

 If you instantiate BUFR as the language template describes, the following syntax error will be reported in synthesis:

[HDL 9-806] Syntax error near "7". 

 

Solution

Double quotes are used on "7SERIES" for SIM_DEVICE in both the Verilog and VHDL template, but only one quote is required.

The correct template should be as follows:

Verilog:

   BUFR #(
      .BUFR_DIVIDE("BYPASS"),   // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" 
      .SIM_DEVICE( "7SERIES" )  // Must be set to "7SERIES" 
   )
   BUFR_inst (
      .O(O),     // 1-bit output: Clock output port
      .CE(CE),   // 1-bit input: Active high, clock enable (Divided modes only)
      .CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
      .I(I)      // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
   );

VHDL:

   BUFR_inst : BUFR
   generic map (
      BUFR_DIVIDE => "BYPASS",   -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" 
      SIM_DEVICE => "7SERIES -- Must be set to "7SERIES" 
   )
   port map (
      O => O,     -- 1-bit output: Clock output port
      CE => CE,   -- 1-bit input: Active high, clock enable (Divided modes only)
      CLR => CLR, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
      I => I      -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
   );

This issue has been fixed in the 2015.1 release.

AR# 63228
Date Created 01/03/2015
Last Updated 01/22/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3