Version Found:RLDRAM3 v6.1
Version Resolved: See (Xilinx Answer 69037)
The following path (or similar paths) may fail timing for MIG UltraScale RLDRAM3 designs as a result of a long route delays or as a result of incorrect speed files used for -1 and -1L devices:
Careful floorplanning can be used to resolve these timing failures.
However, in some cases floorplanning might not resolve the issue, in which case installing the attached tactical IP patch is required.
If you are still unable to resolve the timing failures please open a Service Request with Xilinx Technical Support.
To install the patch, extract the contents of "AR63238_MIG_UltraScale_v6_1_preliminary_rev1.zip" to the 2014.4 install directory (for example, C:\Xilinx\Vivado\2014.4\), then open Vivado 2014.4 and regenerate all of your MIG UltraScale IP.
Note1: This tactical patch is only compatible with the Vivado 2014.4 and MIG UltraScale v6.1 IP.
Note2: Performance_NetDelay_high or Congestion_SpreadLogic_high implementation strategies might need to be applied to close timing with the provided patch.
01/16/2015 - Initial Release
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