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AR# 63240

MIG UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)

Description

Version Found: MIG v6.1

Version Resolved: See (Xilinx Answer 58435)

Within the MIG UltraScale DDR4/3 PHY Only documentation (PG150 > DDR3/DDR4 > Designing with the Core > Protocol Description > PHY Only Interface), the "rdDataEn" signal is described as follows:

"Read data valid. This signal asserts for one system clock cycle for each completed read operation, indicating that the rdData, rdDataAddr, per_rd_done, and rmw_rd_done signals are valid. 

These signals are only valid when rdDataEn asserts. rdData must be consumed when rdDataEn asserts or data is lost. Active-High."

This description should not include "per_rd_done" and "rmw_rd_done" as these will assert separately from rdDataEn.

Solution

The proper usage is for custom controllers to exclusively monitor each of the PHY outputs as follows:

  1. rdDataEn for the return of valid data (rdData and rdDataAddr)

  2. per_rd_done for the return of a read.
    This is used for periodic adjustments, and therefore should be distinct from normal read traffic.

  3. rmw_rd_done for the return of a RMW sequence. This should also be distinct from normal read traffic.


The RTL matches this behavior.

The documentation has been updated to match the RTL and behavior noted within this Answer Record in the v7.0 release of (PG150).

Revision History:

01/07/2015 - Initial Release

AR# 63240
Date Created 01/06/2015
Last Updated 07/13/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale