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AR# 63292

Vivado 2014.4 - Logic Debug - Digilent Cable at 20Mhz ILA not Triggering


When trying to trigger a design with a frequency clock slower than 2x the JTAG clock frequency, the ILA does not trigger.


This is a debug limitation.

The clock driving the design needs to be at least 2x the frequency of the JTAG clock frequency.
AR# 63292
Date Created 01/13/2015
Last Updated 03/19/2015
Status Active
Type General Article
  • FPGA Device Families