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AR# 63303

2014.4 MicroBlaze MCS - I cannot simulate the MicroBlaze MCS in my IPI design


I have a MicroBlaze MCS in my Vivado IPI BD design. 

However, when I try to simulate it, I get an error similar to the following:

ERROR: [VRFC 10-451] cannot open file 'int_infile' [<Vivado Install dir>/data/vhdl/src/unisims/primitive/RAMB36E1.vhd:1100]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit top in library work failed.
ERROR: [Runs 36-25] xelab application returned error(s). Please see '/projects/project_1/project_1.sim/sim_1/behav/xelab.log' file for more details.
ERROR: [Common 17-69] Command failed: Failed to compile the design!

The MEM files are not created and as a result I cannot simulate.

 How can I resolve this?



The steps to simulate the MicroBlaze MCS in Vivado IPI are shown below:


Step 1: Add the MicroBlaze MCS to the IPI design and configure the IP to match your needs.

Step 2: Generate the Output Products.

Step 3: Generate the ELF.

  • Launch SDK
  • In SDK, select File -> New -> Project -> Xilinx -> Hardware Platform Specification
  • In the Target Hardware Specification, Browse to the SDK XML file in the project directory:
    • project_1\project_1.srcs\sources_1\bd\design_1\ip\design_1_microblaze_mcs_0_0
  • You can now create the ELF.
  • Note: this flow is fully documented in the MicroBlaze MCS Product Guide, here

Step 4: Add the ELF file as a simulation source in Vivado.

Step 5: In Vivado, select Tools -> Associate ELF files. Under the Simulation, add the ELF generated in Step 3.

Step 6: Set the SCOPED_TO_REF, and SCOPED_TO_CELLS values for the BMM file.

  • The SCOPED_TO_CELLS is the cell name of the MCS.
  • The SCOPED_TO_REF is the Module name containing the cell.
  • This can be obtained from the sources in Vivado.
    For example:


In the project above, the SCOPED_TO_CELLS is microblaze_mcs_0, and the SCOPED_TO_REF is mcs_test
To set this, use the TCL commands below:


set_property SCOPED_TO_CELLS {microblaze_mcs_0} [get_files *bmm]


set_property SCOPED_TO_REF {mcs_test} [get_files *bmm]



Step 7: Run Simulation.

Verify that the MEM files are generated in the project_1\project_1.sim\sim_1\behav folder.
If they are not generated, please review Step 6.


AR# 63303
Date Created 01/15/2015
Last Updated 03/25/2015
Status Active
Type Known Issues
  • Artix-7
  • Kintex UltraScale
  • Kintex-7
  • More
  • Virtex UltraScale
  • Virtex-7
  • Less
  • Vivado Design Suite - 2014.4
  • MicroBlaze Micro Controller System (MCS)