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AR# 63329

UltraScale Integrated Interlaken Core - 2014.4 - Invalid Reference Clock Distribution when Channels operating above 16.375 Gb/s

Description

(UG578) UltraScale Architecture GTY Transceivers states that Channels operating above 16.375 Gb/s cannot source a reference clock from another Quad and must use one of the two local reference clock pin pairs in its own Quad.

However, when generating the Interlaken core in 2014.4 and earlier,  one reference clock pin pair (gt_ref_clk_p/n) drives more than one quad at rates above 16.275Gb/s.

Solution

This issue was fixed in the 2014.4.1 release.
AR# 63329
Date Created 01/18/2015
Last Updated 03/06/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4