UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63349

My IBERT link is always up when Fast Clk is selected from RX side even when RX pins are unconnected

Description

My IBERT link is always up when Fast Clk is selected from the RX side even when RX pins are unconnected.

Why does this occur?

Solution

On the 7-series GTX there are situations where a link is detected when the RX lines are unconnected.


The feedback loop in the GTX DFE equalization can cause the output to toggle when there is no input on the line.  

This toggling can mimic the fast clock input so that a link is detected when there is no link present.  

The slow clock input and the prbs modes do not exhibit this behavior.



DEFMode.JPG

 

If the first bit is captured as a 1, the DFE tap 1 correction polarity is inverted to 1 x W1 where W1 is the Tap1 coefficient controlled by adaptation. 

If the previous bit is captured as a 0, the DFE tap 1 correction polarity is inverted to 0 x W1.
 

If the RX is not connected, the differential input might floating near the threshold voltage of the Slicer. 

If the polarity of the Tap 1 correction changes every cycle, that feedback will push the floating signal above and below the threshold voltage for the slicer, especially if the Tap1 coefficient (W1) is large.

This happens because the adaptation is being fed incorrect data due to the unconnected input.

AR# 63349
Date Created 01/20/2015
Last Updated 01/26/2015
Status Active
Type General Article
Devices
  • Kintex-7
  • Artix-7
  • Virtex-7