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AR# 63367

Vivado DRC - Incorrect DRC Warning "An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found" if I set two MIO banks to different I/O Standards.


I set LVCMOS33 for MIO bank 0 (bank 500 in package View), and LVCMOS 1.8 for bank 1 (bank 501 in package View). 

After synthesis, I received the following warning during the DRC check:

An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. 
Components associated with this bus are: FIXED_IO_mio[53] of IOStandard LVCMOS18; ... FIXED_IO_mio[15] of IOStandard LVCMOS33 ...

After I open it in PinPlanning, it does not show MIO pins in any banks, and so all of the FIXED_IO_MIO pins are considered the same group. 

How can I resolve this problem?


This is a known issue in the Vivado PinPlanning tool.

In order to work around the issue, the DRC checks need to be disabled. 

The current workaround is to use the following Tcl command to disable the DRC check :

set_property IS_ENABLED 0 [get_drc_checks PLIO*]
AR# 63367
Date 05/28/2015
Status Active
Type General Article
  • Vivado Design Suite
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