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AR# 63368

JESD204 - What simulation timescale is used in the JESD example deisgn testbench?


When running the JESD024 example design simulation, what timescale is used in the associated testbench?


The JESD204 example design testbench uses a timescale of '1ps.

Some frequencies are rounded to ensure that the bit period of the serial data is a whole number of ps.

Changing the timescale may result in inaccurate results, or simulation failure.

AR# 63368
Date Created 01/21/2015
Last Updated 01/22/2015
Status Active
Type General Article
  • JESD204