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AR# 63368

JESD204 - What simulation timescale is used in the JESD example design testbench?

Description

When running the JESD204 example design simulation, what timescale is used in the associated testbench?

Solution

The JESD204 example design testbench uses a timescale of '1ps.

Some frequencies are rounded to ensure that the bit period of the serial data is a whole number of ps.

Changing the timescale might result in inaccurate results, or simulation failure.

AR# 63368
Date 10/06/2017
Status Active
Type General Article
IP
  • JESD204
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